This invention relates generally to the field of integrated circuits and, more particularly, to an improved procedure for erasing Flash Electrically-Erasable, read-Only Memories (Flash EPROMs). The type of Flash EPROM to which this invention relates has nonvolatile memory cells formed from a single transistor, the single transistor formed without a split control gate.
Using early prior-art procedures, all of the memory cells of a nonvolatile Flash EPROM array are erased simultaneously. In many cases, the simultaneous erasure results in the over-erasure of an excessive number of memory cells. One solution to over-erasure of an excessive number of memory cells is a later prior-art procedure in which subarrays of the entire array are separately erased.
In the later prior-art procedure, erasing pulses are simultaneously applied to all of the cells in all of the subarrays of a nonvolatile Flash EPROM array. After each erasing pulse is applied, a corresponding cell, or corresponding group of cells, in each subarray is checked to see whether or not that cell, or group of cells, is erased. Upon finding that a cell, or group of cells, is erased, no further erasing pulses are automatically applied simultaneously to all of the cells in all of the subarrays. The test continues to determine whether or not corresponding individual cells, or groups of cells, in each subarray are erased. If any of the corresponding cells, or groups of cells, is found not to be erased, at least one erasing pulse is applied only to those subarrays containing the non-erased cells. At each step, the over-erased cells of each subarray are corrected and the erasing procedure continues until all of the cells are erased, but not over-erased, or until a count is exceeded.
A problem arises when using the later prior-art procedure to erase a nonvolatile Flash EPROM with many slow memory cells. Under that circumstance, the later prior-art procedure requires an excessive amount of time for completion of the erase operation.
There is a need for an improved erase procedure that includes the flexibility of erasing individual subarrays, but that decreases the amount of time required for completion of the erase operation, yet results in a narrow distribution of threshold voltages.